A current common requirement for an advanced electronic circuit and particularly for circuits manufactured as integrated circuits (“ICs”) in semiconductor processes is the use of embedded or discrete memory devices. Increasingly these memory devices are provided as a macro or portion of an integrated circuit and manufactured on a substrate along with other circuitry such as user defined logic circuitry, microprocessors, microcontrollers, digital signal processors and the like to provide a highly integrated circuit in a single package. Embedded memory arrays may be formed as dynamic random access memories (DRAMs) or increasingly as static random access memories (SRAMs). While DRAM cells require less silicon area per stored bit, the DRAM cells require sophisticated memory controllers to perform the periodic refresh cycles needed to maintain the data over time. In contrast, while SRAM cells require more silicon area per stored bit, the SRAM cells will maintain the data without the need for refresh cycles and therefore are better suited for some embedded applications. As alternatives, non volatile memory cells such as FLASH or EEPROM cells may also be embedded with other circuitry.
In order to make a memory cell as small as possible and to make read and write cycles as fast as possible, memory cells are created using small signal approaches. A capacitive charge is stored in the cell either in a discrete capacitor such as for a DRAM cell, or using the gate capacitors and the latching action of cross coupled inverters, such as for an SRAM cell. By keeping the signal levels small, the cell may be rapidly read from and written to.
However, the small signals on the bit lines are not useful by other logic circuitry and so these small signal levels are usually converted to full logic signals in the input/output circuitry of a memory array. This function is performed through the use of differential sense amplifiers. These differential sense amplifiers sense a small signal difference between an active bit line, which is coupled to a selected memory cell, and another bit line, which is not selected and so maintains a level voltage. The differential voltage is used to cause the sense amplifier to put out a voltage corresponding to a logical “1” or logical “0” depending on the stored bit in the cell. Typically a cell storing a logical “1” will leave the bit line undisturbed, while a cell storing a logical “0” will discharge, or lower the voltage on, the respective bit line, causing a small voltage drop. The small voltage drop is then sensed by the differential sense amplifier.
The read speed of a memory device is a critical characteristic of a high density memory array performance. The speed for a read cycle is determined in part by the time required for a bit cell to discharge the nominal voltage on the bit line. If the bit lines are particularly long and/or heavily loaded, that is, the bit lines have many memory cells coupled to them, the read time may become unacceptably long.
FIG. 1 depicts a simple DRAM cell 10 of the prior art. An access transistor T1 is coupled with its gate input coupled to a word line WL. Although not visible in the figure the word line WL will be coupled to many other memory cells along its length. When the word line WL goes active (that is when a rising voltage is supplied on the word line) the access transistor T1 turns on and couples one plate of the storage capacitor C1 to the bit line BL. Although the bit line BL is also coupled to other memory cells, the memory array is arranged so that in a given cycle only one memory cell is active on a particular bit line. As can be seen from the figure, if the capacitor C1 is charged, storing data representing, for example, a logical “1”, the bit line which begins the memory cycle in a “pre-charged” state, will remain at a high voltage level. If on the other hand the capacitor C1 is discharged, meaning it is storing data representing a logical “0” then as the word line goes active and the transistor T1 couples the memory cell to the bit line, a charge sharing event occurs and the bit line voltage will fall slightly as the capacitor C1 takes charge from the bit line. This will put a lower voltage, representing a logical “0”, on the bit line.
Because the sense amplifiers used in typical memory devices are small signal sense amplifiers, during a read cycle the bit line voltages are moved only slightly below a pre charged voltage, or not changed at all. The use of two bit lines, one active and one inactive, input into a logical gate sense amplifier or a differential pair sense amplifier, enables fast sensing of the read data. It is not necessary to wait for the bit line to reach a full high or full low logic voltage to obtain the data, instead the small signal difference is detected and the sense amplifier, which outputs a full logical level voltage, amplifies this value to a logic level voltage for use by other circuits in the device.
FIG. 2 depicts an exemplary prior art memory array architecture. As is known to those skilled in the art, memory arrays may vary widely in size and may include millions of bit cells, for example a 16 megabyte memory has 16 million cells. These may be arranged in many sub-arrays and each of those may be further divided. The use of illustrative embodiments in this description which depict, for ease of understanding, only a few bit cells is not limiting on the discussion, or the embodiments of the invention.
In FIG. 2 the illustrative memory array is divided simply into two sub-arrays, a left sub-array 11 and a right sub-array 13. There are bit lines coupled to a sense amplifier 15 which may be positioned, for example, in a central portion between the two sub-arrays, forming part of a local input/output or “local I/O” circuit. The sense amplifier 15 is shown implemented as a differential signal sense amplifier with bit lines and cells arranged running right to left. In some prior art literature the bit lines are referred to as forming “columns” and the word lines are said to form “rows” of cells which are arranged along the word lines. In using a memory array, data words are usually input to, and output from, the memory. A data word has a word width; it might be 16 bits, 32 bits, 64 bits, 128 bits. The word line, when active, will cause the cells that form a word at a selected row to become active. There will be a sense amplifier for each bit, or each column, in the data word. Each sense amplifier is coupled to an active bit line and also to an inactive one to form the differential voltage comparison needed to sense the small signal voltage. In a memory read operation, the bit lines are first precharged to a nominal voltage. Often, to reduce the power and speed the transitions of the bit lines, the precharge voltage is substantially less than a nominal positive supply voltage, for example precharge voltages such as Vdd/2, or some other reduced voltage, might be used.
The sense amplifier can sense a difference voltage of as little as a few millivolts. The use of small signal voltages on the differential bit lines can reduce the size of the storage capacitor needed, and speed up the read access time for the memory. However the small signals used have to be selected to be large enough to prevent data read errors, and to overcome noise and coupling signals from adjacent bit lines, for example.
Because memory arrays can be physically laid out in any fashion including folded and mirror image arrangements, the terms “rows” and “columns” do not really describe orthogonal arrangements, even though in the simple schematic views such as the ones used here the column or bit lines and row or word lines are usually drawn in this manner. In a physical implementation the bit lines and word lines can be in parallel, orthogonal, or arranged at any angle to each other. The figures presented here are simplified schematic views that are used to discuss the circuit, but which do not reflect the manner or in any way limit the manner of a physical implementation of the device.
In FIG. 2, there are “n+1” memory cells ranging from Cell_0 to Cell_n in each sub-array arranged along each bit line position, each cell is coupled to one of the corresponding bit lines, the left or the right bit lines BL_L and BL_R. For very large memory arrays (high density memory devices) the bit lines can become quite long, and an additional capacitive loading occurs for the extra length of the physical conductor that forms the bit line and for each added memory cell that is coupled to the bit line. During a read operation, because the selected memory cells must discharge or “charge share” with the bit lines in order to change the voltage on the bit lines, the capacitance on the bit line is critical to the amount of time it takes the cell to change the bit line voltage and therefore to put data on the bit lines. As the bit line capacitance increases, the time needed to perform a memory read access cycle also increases, and for larger memory arrays this read access time may become unacceptably long.
One skilled in the art will recognize that the bit line length and loading effects occur with all types of memory cells. The example DRAM type cells of FIG. 1 are easily the smallest memory cells; however, they also impose additional timing requirements on an integrated circuit. The read cycle for a DRAM cell must also include a “write back” cycle, because the DRAM reads are destructive (the cell discharges the bit line directly which changes the state of the cell, so to maintain the data, the DRAM cell must be rewritten to restore it to the original state.) For reliable operation, the DRAM cells also have to be “refreshed” fairly frequently, a refresh is a read, followed by a write back, of all of the cells. This refresh of dynamic memory is performed periodically; else the stored data can be lost due to capacitor leakage from the cell storage capacitors. An integrated circuit with embedded memory must also include support logic that performs these time critical operations.
Accordingly, other memory cells for storage are increasingly typically used, such as six transistor (6T) or eight transistor (8T) static RAM cells. These SRAM cells form a latch that is constantly supplying power to the stored capacitive charge, and thus they do not require refresh cycles. The use of SRAM cells imposes less timing requirements on the integrated circuit or system. Read cycles of SRAM cells are also not destructive. The static characteristic of these cells may be particularly important in applications for battery powered devices, where, in order to extend battery life, integrated circuits often go into “standby” or “sleep modes”, in those modes DRAM cells are not able to retain data, so an SRAM memory array is a more attractive option. However, the silicon area per bit for an SRAM cell is somewhat higher than for a DRAM cell, simply because the number of transistors is larger (6T for SRAM, vs. 1T for DRAM).
Regardless of the type of memory cell used, the memory arrays are increasing in capacity, and thus in physical size, which tends to increase the length of the bit lines, and also the number of cells attached to a bit line.
FIG. 3 depicts in a simple schematic view another prior art example memory architecture. Here the memory device 12 uses a different type of sense amplifier 18. In this example, a single ended logic gate sense amplifier 18 is used. The remaining elements of the memory array are again arranged as shown in FIG. 2, and like reference numerals are used for the left sub array 11, the right sub array 13, and the cells 17 which again have a cell pitch height “h”. As shown in FIG. 3, the sense amplifier 18 performs a logical NAND function, that is, the data output signal “SA-out” will be a high value when either input, whether from the left bit line BL-L or the right bit line BL-R, is a low voltage.
In a memory operation, the bit lines BL_L and BL_R are first precharged to a higher (although not necessarily a full positive voltage supply level) voltage before the memory cycle begins. The memory cell selected will either leave the bit line voltage undisturbed, or slightly discharge the bit line to a lower voltage. In this way the active bit line may be a small differential voltage that represents a “1” (typically, this bit line voltage is at or above the pre-charge voltage level) or a “0” (typically, the bit line voltage is slightly lowered from the precharge level), while the inactive or unselected bit line remains at the nominal precharge voltage. This characteristic of pairing a selected bit line with an unselected bit line allows the detection of the small signal voltage difference between the two bit lines. In this sense the NAND gate acts as a logical comparator and outputs a “1” when a voltage difference is detected between the two bit lines BL_L and BL_R. Since only one of the two bit lines is active, the data from the active bit line is thus correctly sensed, and amplified onto the “SA-out” data signal. The output signal is a full logic voltage so that other circuitry can correctly receive it. Thus, a sense amplifier first “senses” the small signal voltage and then “amplifies” it to an output.
An important characteristic of the sense amplifiers used in memory arrays is that they should be physically configured for a dense memory layout. A distance “h”, shown in both FIGS. 2 and 3, represents the bit cell pitch in one direction for the memory cells arranged in an adjacent manner to form a column; “h” is the cell pitch “height”. In order to compactly lay out the memory array, the sense amplifiers, one of which will be provided for each bit line column, should have a pitch height that is the same or less than the memory cells. By keeping the pitch regular, the memory array may be densely compacted, the lay out is regular and orderly, and the memory array uses silicon area as efficiently as possible.
One approach known in the art to shorten bit line swing times is to add additional sense amplifiers for each column, and to divide the bit lines into segments; however, this approach reduces the layout efficiency obtained, as the added sense amplifiers don't fit in the regular cell pitch structure defined by the cell pitch height, and so while some speed benefit in bit line swing time may be obtained, the disadvantages created by the extra silicon area penalty when these divided bit lines are used are undesirable.
In the typical prior art memory devices, the long bit lines that result from the memory array architectures in high density memory arrays greatly increases the time needed for a memory read access. As a result read speeds for the high density memory arrays are undesirably slow. These problems are increasing as memory array density (the number of bits) increases.
A continuing need for memory bit line architectures that provide reduced bit line loading and fast read access times in large memory arrays, and for methods for these memory devices that reduce or eliminate the problems associated with the prior art circuits and methods thus exists.